1. Field of the Invention
Generally, the present disclosure generally relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of tailoring the work function characteristics of semiconductor devices that have a gate structure comprised of a high-k layer of insulting material and a layer of metal by implanting fluorine into the gate structure.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET (whether an NFET or a PFET) is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. A gate insulation layer is positioned between the gate electrode and the channel region that will be formed in the substrate. Electrical contacts are made to the source and drain regions, and current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If there is no voltage applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region. Traditionally, FETs have been substantially planar devices, but similar principles of operation apply to more three-dimensional FET structures, devices that are typically referred to as FinFETs.
For many early device technology generations, the gate structures of most transistor elements have been comprised of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate structures comprised of alternative materials in an effort to avoid the short-channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 14-32 nm, gate structures having a so-called high-k dielectric/metal gate (HK/MG) configuration have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide/polysilicon (SiO/poly) configurations.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate insulation layer in HK/MG gate structures. For example, in some transistor element designs, a high-k gate insulation layer may include tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicates (HfSiOx) and the like. Furthermore, one or more non-polysilicon metal gate electrode materials—i.e., a metal gate stack—may be used in HK/MG configurations so as to control the work function of the transistor. These metal gate electrode materials may include, for example, one or more layers of titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi) and the like.
FIG. 1 depicts one illustrative example of a prior art transistor 10 with a HK/MG gate structure 22. As shown in FIG. 1, the basic transistor structure is formed in and above a semiconducting substrate 11 in an active area defined by a shallow trench isolation structure 13. At the point of fabrication depicted in FIG. 1, the gate structure 22 of the device 10 includes a silicon dioxide gate insulation layer 12 having a thickness of about 1 nm, a layer of hafnium oxide 14 having a thickness of about 1.7 nm, a layer of titanium nitride 16 having a thickness of about 1.5 nm and a work-function adjusting layer of metal 18 having a thickness of about 5 nm. The work-function adjusting layer of metal 18 may be made of a variety of different metals, such as aluminum (Al) for PFET devices or lanthanum (La) for NFET devices. Also depicted in FIG. 1 is an illustrative protective gate cap layer 23 (e.g., silicon nitride), illustrative sidewall spacers 24 (e.g., silicon nitride), a layer of insulating material 26 (e.g., silicon dioxide) and a plurality of source/drain regions 15 that are formed in the substrate 11.
The various components and structures of the device 10 may be formed using a variety of different materials and by performing a variety of known techniques. For example, the source/drain regions 15 may be comprised of implanted dopant materials (N-type dopants for NFET devices and P-type dopant for PFET devices) that are implanted into the substrate using known masking and ion implantation techniques. Of course, those skilled in the art will recognize that there are other features of the transistor 10 that are not depicted in the drawings for purposes of clarity. For example, so-called halo implant regions are not depicted in the drawings, as well as various layers or regions of silicon germanium that are typically found in high-performance PFET transistors. In some cases, layers of metal other that the titanium nitride layers may be employed in such devices and other high-k insulation materials may be used in the device 10 instead of the depicted the layer of hafnium oxide 14.
The amount by which the threshold voltage of the device 10 may be lowered depends, at least in part, upon the amount of the work function metal, e.g., aluminum or lanthanum, that diffuses to the interface between the layer of silicon dioxide 12 and the layer of high-k insulating material 14. The amount of the work function metal present at the interface also may degrade the charge carrier mobility of the devices.
The present disclosure is directed to various methods of tailoring the work function characteristics of semiconductor devices that have a gate structure comprised of a high-k layer of insulting material and a layer of metal by implanting fluorine into the gate structure that may avoid, or at least reduce, the effects of one or more of the problems identified above.